Aside from the reset exception, it has the highest priority of all exceptions. If errors happen in other exception handlers, an NMI will be triggered.
Non-Maskable Interrupt (NMI): As the name suggests, this interrupt cannot be disabled. Pended System Call (PendSV): Operates with SVC to ease RTOS development as it’s intended to be an interrupt for RTOS use. This provides protection for critical system functionalities. it allows non-privileged software to make system calls. System Service Call (SVC): Similar to SVC instruction on other ARM cores. 
Reset: This is the handler routine that gets executed when the processor gets out of a reset state whatever the source is.
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Allows another pending interrupt to be serviced without a full restore/save for processor context (this feature is called tail-chaining)Įxceptions can be fired by various events including:Įxceptions that get fired by an internal source to the system and not by any external hardware or peripherals. Allows late determination of highest priority pending interrupt. Automatically saves and restores processor context. The interrupt entry and exit are hardware implemented in order to reduce the latency and speed up the response. Handler Mode: Which is entered on all other exceptions. Thread Mode: Which is entered on reset. And it can be in one of the following modes: The processor mode can change when exceptions occur. The interrupt architecture and priorities are very flexible and highly configurable to support RTOS. 
Which offloads this work overhead from the CPU. Micro-Coded Architecture So that interrupt stacking, entry, and exit are done automatically in hardware. Which includes the Nested Vectored Interrupt Controller (NVIC). ARM ® v7 Cortex™ Exceptions / InterruptsĪRM v7 Core supports multiple great features for handling exceptions and interrupts.
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